High speed electronic logic systems are often comprised of a mixture of silicon integrated circuit (IC) technologies. A system may be formed of complementary metal oxide silicon (CMOS) field effect transistors (FETs), transistor-transistor logic (TTL) transistors, or emitter coupled logic (ECL) devices. A system designer will choose the best silicon IC technologies, in terms of cost or performance, for each function of the system being designed. For example, medium to low-speed computational functions have been found to be better implemented in CMOS, high speed serial functions have been found to be better suited for ECL, and TTL is used where moderately high-speed is required but the extra complexity of ECL is not warranted.
Connecting sub-systems that use all of these silicon technologies is difficult. A CMOS to ECL interface poses a particular challenge, because of differences is logic voltage swings and power supplies. Typically, CMOS logic voltage swings between +5 volts for a logical "1" and 0 volts for a logical "0". On the other hand, ECL data signals swing between -0.8 volts for a logical "1" and -1.8 volts for a logical "0". CMOS devices are nominally powered with a 5 volt supply, and ECL devices are powered with a -4.8 to -5.2 volt supply. Therefore, the system designer has power supply, voltage swing, and logic level reference level problems when an attempt is made to create CMOS to ECL interfaces in a design. CMOS output signals must be translated to be suitable for use with standard ECL devices.
Part of these problems can be solved if the system designer chooses to power ECL devices with the same 5 volt power supply used for the CMOS and TTL devices. The VCC terminal of the ECL circuit is connected to 5 volts, and its VEE terminal is connected to the system ground. While ECL devices are very susceptible to noise on their VEE rail, if this rail is decoupled well and if differential devices are used, this powering scheme has been found to be tractable.
A remaining problem, however, is to create a CMOS output with logical swings that match that of an ECL device relative to the 5 volt, or VDD supply rail.
In the article "ECL-CMOS and CMOS-ECL Interface in 1.2.mu.m CMOS for 150-MHz Digital ECL Data Transmission System", IEEE Journal of Solid-State Circuits, Vol 26, No. 1, January 1991, by Michael S. J. Steyaert, et al, a circuit is described in which high speed current switches are controlled by a replicated bias scheme. However this circuit requires an external termination voltage supply, and its output driver has been found to be unstable under some conditions.